Project: A Low Cost MIDI Fast Response Configurable Step Sequencer, design and implementation.

Place of Development: Faculty of Engineering - University of Buenos Aires/CAT Recording Studios
Date: June 2010
Duration: 4 weeks
Author: Pablo Manuel Delgado

References:

[1] MacKenzie, S. The 8051 Microcontroller, Third Edici on, Prentice Hall.
[2] Datasheets for: AT89S52, 81C55, Winstar Display WH1602C-B, MAX232C,
CD74HC244E.
[3] MIDI Implementation Standard
[4] Messick, Paul. Maximum MIDI: Advanced music applications in C++, Manning Publications.

Video Demonstration

The main goal of this project was to design, develop and implement a MIDI based real time event sequencer with an 8051 microcontroller.
This device has the capability of communicating with other external equipment which support this protocol and establishing a synchronized execution of the diverse events on different machines by doing so.
The most well known application of this kind of devices is the cyclic sequencing and synchronization of different electronic musical instruments at a determined pace. Other applications include lightning and special effects for a great variety of performances.
The market price of a professionally available product of these characteristics is relatively high, so that special care was taken in proposing an economically viable and efficient alternative to these complex industrial solutions, a task specially suited for low cost microcontrollers in the 8051 family. Additional functionality was added:

• PC Device communication for sequence preloading.
• Protocol parameter configurability

Project description

Introduction

The sequencer's main function is that of executing diverse rigid patterns of events by utilizing an 8, 16 or 32 step grid. These patterns are chained and modified in real time in order to conceive complex compositions. The sequence is generally displayed with some indicator in the step matrix (see figure below). The number of rows can vary and it generally represents a fixed musical note or percussive element, the final row quantity will determine the amount of events that can be triggered at the same time. Due to the cyclic nature of this process, this device is usually utilized on the generation of rhythmic patterns and periodic musical phrases.

Figure 1: Step sequencer operation

Communication with sequenced devices

One of the project's fundamental characteristics is that of inter-compatibility with different external agents to be operated. The device itself has not got any means of sound synthesis but acts as a mere event generator within the protocol standard. This communication is produced by using the micorcontroller's serial port with a software generated baud rate. 
The MIDI (Musical Instruments Digital Interface) communication protocol is widely used within the industry and is a standard for event intercommunication between computers, synthesizers, sound cards, lighting devices and effect units. Signals created comprise volume changes, vibrato and signal panning, clock synchronization and tempo. Due to the great variety of implementations available, it is common practice for these devices to include a MIDI implementation table exactly specifying how these parameters are handled and communicated in every particular case.

Figure 2: Device interconnection example.

Protocol's basic structure

The MIDI protocol consists on a start bit-stop bit serial interface communication for data transfer. It's baud rate is specified in 31250 symbols per second up to 1% of tolerance. Internally, MIDI comprises 16 channels (0 to 15) for media and control parameters multiplexing.
The basic structure used for the MIDI messages consists of 3 bytes. The first one being dedicated to system and channel messages (i.e. Channel 1, NOTE ON, Channel 3 NOTE OFF, hi of low nibble control type) and the second one containing the note number for the different octaves (coded onto 255 bytes). The third byte is dedicated to velocity and aftertouch for supporting devices. 
For example: a "Note ON" message on Channel 1 (0 Nibble), 0x3C note (C3 on the tempered scale) with an intensity (aftertouch value) of 0x34 would be:

0900H 003CH 0034H


Features and Configurability

The following features are foreseen for the project:

• Text only LCD display and a multiple level menu for parameter configuration.
• LED based current state indicator.
• 4x8 keyboard with a logical state indicator for each button (on/off).
• Configurable tempo from 60 to 200 Beats Per Minute.
• Instrument type or MIDI note for each row.
• Volume control (after-touch).
• Serial port and USB port support for loading premade sequences from a personal computer.

Microcontroller choice and peripherals

Facing the diverse needs specified on the previous sections, a technical and market-related investigation was carried out in order to define which device would be the most suitable for this project and meet the most project requirements. The requirements, so to speak, were:

• At least three independent timers to generate robust sequencing, MIDI baud rate and serial/usb communication baud rate synchronization. 
• Enough ROM memory for code storing, definitions and equivalency tables for tempo, menu items and configurable variables.
• Argentinean market availability and price.
• Is situ parallel programming capability, due to simplicity and cost.
• Great amount of available ports to handle the different ins and outs (keyboards, LED arrays, display, etc.).

The 89S52 microcontroller instantly met at least the first four requirements, whilst the last two were met by adding two hardware port expanders with extra ROM memory included.  

It must be noted that there is not a single optimal choice for the microcontrolling device. There are at least two other suitable architectures for this kind of task. Nevertheless, the 8051 architecture has a vast amount of documentation and market availability. Albeit a steeper learning/programming curve, the fact that its low level (assembler) programming is specially well suited for real time application optimization was enough to ensure an overall robustness in the products performance. Many commercially available MIDI implementations lack this robustness and user response, and that is undoubtedly a determinant factor on the final product's quality.

Tempo and execution rate calculation

BPM and instruction execution rate

The execution pace of a musical sequence or piece is defined in Beats Per Minute (BPM). In order to set a proper correspondence between the timer's hardware interrupt ratio assigned for the step sequence pace and the BPM value, a BPM conversion formula was derived:

\begin{equation}
\alpha = \frac{60 \times 1MHz.}{BPM \times \beta}
\end{equation}

$$\alpha$$ is the amount of interruptions that occur before the processor's core moves on to the next step on the sequence and
$$\beta$$ is the reload rate of the timer per interruption.
For better precision, a data fitted version of the Beta parameter curve was used to show the hyperbolic function variations (Figure 3). The black curve represents the "continuous" values while the white ones represent the values implemented on the ROM equivalence lookup table.

Figure 3: Timer 0 interruption rate vs time. Real curve and lookup table values.

Technical Specifications

• Protocol: MIDI Standard v1.0 and RS-232/USB
• Physical Interface: DIN5/180º connector, DB-9 Male Input
• Power Supply: 7-9 V (5v regulated internally), 250mA
• Display: 16 character alphanumeric x 2 
• Keyboard: 4x8 push button matrix and LED binary indicator, Menu navigation, Play, Pause buttons

Block Diagram

A comprehensive block diagram is shown on  Figure 4.  The core of the project is comprised by the microcontroller and the port expanders. The arrows show the data flow direction from device to peripherals.

Figure 4: Block Diagram

Circuit

Schematic Diagram

Figures 5, 6 and 7 show the electrical connection schematics for the microcontroller's printed circuit board, the matrix keyboard, the LED array and the menu keyboard respectively.

In order to ameliorate bus noise immunity on the LCD, pull up resistors were used on each bus connection to make the high and low logical states (voltage levels) more reliable.
At first, serial resistors were calculated for the LED array implementation. The leds on the matrix are not actually on all the time, but they blink on and off at a very fast rate on each microcontroller cycle depending on their logical state. As a consequence of this mode of operation, these previously calculated serial resistors limited the amount of intermittent current that was necessary to give the LEDs a proper brightness, so they were omitted on the final stage of the design.
The MIDI interface was established by means of a current loop specified in the MIDI standard. An impedance matching buffer on the 89S52 serial output was used.

Figure 5: Microcontroller connection diagram.

Figure 6: Matrix keyboard and led connection diagram.

Figure 7: Menu navigation keyboard connection diagram.

PCB

Figures 8, 9 and 10 show a possible design of the printed circuit board. Experimental prototyping boards were used for the first design stages, with the exception of the matrix keyboard and LED, which designs were directly applied onto PCBs after a software schematic/layout matching test.

Figure 8: Main board PCB layout.

Figure 9: Matrix keyboard and LED array PCB layout.

Figure 10: Menu navigation keyboard PCB layout.

Memory Mapping

The external RAM memory mapping is comprised of the memory addresses offered by the 81C55 port expander IC's. Although the internal expander memory was not used in the end, a decision was made to include on the overall project memory design and addressing in case of a future firmware update/product expansion without any hardware modification.

Table 1: Internal Memory Mapping of the 81C55 port expanders.

Table 2: Internal Memory Space of the 81C55 port expanders.

Code Walkthrough

Initializations

The code consists of a series of initializations that can be divided onto three categories:

• Port expanders
• LCD display
• Memory allocation for program variables

Port expanders:

The 81C55 port expanders need a proper initialization in order to be properly used. From the microcontroller's point of view, these are no other than external memory addresses. In turn, these expanders have 255 bytes of RAM memory, a timer, two input/output ports (8 bits) and a third 6 bit communication port. The initialization routine writes a "Command Register" byte that specifies the expander's mode of operation, including port functionality and timer.  This "command register" byte can be modified at any time of the main program execution. 

LCD Display:

A standard initialization routine proposed by the manufacturer is used. This routine is called twice in the code, in order to ensure that the proper values were set for the LCD display, this procedure was determined empirically. The routine's complexity was given by the proper access/write time management due to the fact that this device's frequency of operation orders of magnitude lower than the microcontroller's (270 KHz vs. 12 MHz.)

Variable Initialization:

This routine is just for setting preloaded variable values for the rest of the code. Some subroutines need some variables written on a specific physical address, as well as pre cleansing of memory allocation spaces to avoid garbage information to be permeated on some of the devices' initialization.

Main Routine

As both the sequence and the 89S52 input port comprises of 8 steps and pins respectively, it logically follows that each step (matrix column)  can be read directly from an input port pin. The matrix keyboard consists of 5 rows and 8 columns as well. The four first button rows correspond to the step sequencer and the last row is assigned to the menu navigation keyboard. 

First, the row to be read is addressed by putting a logical zero on the correspondent input pin. Next, the port corresponding to each column is read, a logical zero is assigned each time a button remains pressed. This byte is then complemented and stored into the RAM in an auxiliary array. This method is used because the keyboard is read twice in total, and a logical comparison between the first reading and the second one is performed. In case that the second reading matches the first one, it is considered that the button is on the correct state. This is made so to avoid incorrect state transitions due to the bouncing voltage effect on the push buttons.

Example of a contact's bouncing voltage measurement.

Source: http://mbed.org/users/4180_1/notebook/pushbuttons/

 The comparison is performed on an AND logical gate between the stored readings and the new ones. The state transition update is made by an XOR logical gate with the keyboard's values previously stored. This is made so because the push button logical state is held by software.
A difficult task to accomplish was that of having to read the push button twice with a minimum idle time (approx 10 ms to wait for the bouncing time transient) without having to stop the main routine, due to the real time constraints of the performance. This problem was solved by the use of flag bits and a decrementing auxiliary variable that changed its value each time the processor's core performs a full running cycle.

The algorithm for the push button interaction is described as follows:

1. Read the button's current state. Set flag for the first reading. The first reading won't be repeated until this flag is set low again (first reading semaphore).
2. Wait for the main program loop to decrement the auxiliary variable until it reaches the zero value. (this is equivalent to waiting a prudential time for the second reading)
3. Read the keyboard matrix a second time. Set flag for the second reading. The second reading won't be repeated until this flag is set low again (first reading semaphore).

The reading flags are only set low again when the button is not pressed. This is a mean of avoiding swtiching the state of the push button while it is held pushed and the main loop is not interrupted.

Menu

The menu consists, broadly speaking, of two parts:

• Parameter selection  to be modified.
• Modification of the parameter itself.

 For the parameter selection, a cyclic counter is used. This counter is used as a menu pointer for all the different options to be displayed on the menu. When a parameter is changed, the aforementioned pointer is used to jump into the corresponding change routine. The AJMP instruction is utilized to give the compiler a certain freedom to manage these kind of jumps at the compiling stage. Furthermore, a relative code segment was to be defined in order to establish an INPAGE menu operation. This last step was implemented so to ensure the correct operation of the AJMP instruction.



Here is another video capture showing different parameter configurations via menu navigation. It is also shown how the real time communication with the PC works on loading pre-arranged patters from a file.

Project: A real time closed loop control system and target identification through Ethernet. Design and implementation.

Place of Development: École Nationale Supérieure d'Ingénieurs de Caen- France
Date: September 2012
Duration: 9 days
Author: Pablo Manuel Delgado et al. 

Further reading on J3eA , Volume 12 (2013) (French): http://www.j3ea.org/articles/j3ea/abs/2013/01/j3ea13011/j3ea13011.html

This intensive project took place on the laboratories of ENSICAEN's Signal, Control, Telecommunications and Embedded Systems specialization (SATE) and it comprised several phases distributed in nine full days of work.
The goal was to implement a closed loop control system on a direct current motor whose parameters were passed in real time through Ethernet, in a few longer than a week's time. A group of six people was assigned for this task.

 
The system specifications:

• A real time control algorithm (and a prior system parameter identification) to be run on a PC, the processed data must be transmitted to a microcontroller through Ethernet, which in turn controls the current motor by a PWM output.
• A human-machine graphical interface with all the necessary commands to run the control program.
• The processing paradigm on the micro controller must be real time i.e. preemptive task scheduling. 

 Technological constraints:

• The microcontroller (MCU) has to be a PIC32MX795F512L from Microchip, due to availability reasons.
• The program was developed on IDE MPLAB with a C 32 toolchain.
• The speed measurements are made with an ADC7634 Analog to Digital Converter from Analog Devices linked to the MCU through SPI in order to minimize the final PCB layout.
• The control signal generation is made through a PWM module embedded in the microcontroller. Signal filtering is performed to adapt the controlled system's input requirements. The slow dynamics and noise immunity of the system allow such solution. 
• The PC-MCU communication will be implemented on the TCP/IP protocol.

Technical Specifications:

PIC32MX795F512L

• TQFP 100 pin package
• Core working frequency: 80 MHz
• Peripheral reference working frequency: 40 or 80MHz
• Used peripherals set optimization

ADC AD7634

• Sampling frequency: 2 KHz
•  Bit depth: 18 bits
• Input dynamic range: +/- 10 V (unipolar power supply)
• SPI digital interface for configuration and data communication
• Physical configuration of the ADC's parameters is possible

PWM Signal Conditioning Circuit

• PWM switching frequency at 2KHz and a 3,3V peak to peak amplitude
• Second order Low Pass Filter with a 200 Hz cutting frequency with unity gain on the passband. Its purpose is to reject the PWM signal's higher order harmonics.
•  Adjustable gain for a correct utilization of the motor's control input dynamic range

 PC to MCU link

• TCP/IP protocol. TCP and UDP connection options must be available due to different requierements on the system control parameters' reaction speed. 
• Dynamic IP (DHCP) implementation to ensure greater portability and configuration.

 



Functional Diagram

Task Processing Diagram

Project: An Adaptive NLMS Algorithm for a MVDR Beamformer, design and performance analysis.

Place of Development: University of Buenos Aires - Faculty of Engineering
Date: November 2011
Author: Pablo Manuel Delgado

References:

[1] (Updated )Razia, S; Hossain, T; Matin, M A, "Performance analysis of adaptive beamforming algorithm for smart antenna system", IEEE International Conference on , Informatics, Electronics & Vision (ICIEV), 2012
[2]Kammoun, I.; Jaidane, M., "Exact performances analysis of a selective coefficient adaptive algorithm in acoustic echo cancellation", IEEE International Conference on coustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01). 2001
[3] S. Haykin, Adaptive Filter Theory, Third Edition, Ch. 5 and 9, Prentice Hall.
[4] L. Rey Vega, H. Rey, S. Tressens, J. Benesty. Adaptive Filtering: Algorithms and Analysis.

(MATLAB Testing Code soon to be available) 


A Normalized Least Mean Squares adaptive filter algorithm for an antenna array was implemented and analysed through simulation and real time performance for a QPSK modulated, 1 GHz carrier received test signal. The spatial filter response on the converging period was also determined and compared to that of the first steps of the iteration. A SNR, INR performance sensitivity analysis was also carried out through symbol interference and scattering diagrams.

Antennas (and antenna arrays) often operate in dynamic environments, where the signals (both desired and interfering) arrive from changing directions and with varying powers.
These antenna arrays employ an adaptive weighting algorithm, that adapts the weights based on the received signals to improve the performance of the array.
 
The project consisted in analysing incoming far field band limited signals to an array of antennas of arbitrary number.
The following preexisting conditions were taken into account for the design experiment:

• The arbitrary number M of  antennas were separated at least at a half of the wavelength of the signal of interest, this is a direct consequence of the spatial sampling theorem.

• The signal of interest impinges on the array at an angle of \( \theta_0 = \frac{\pi}{2} \) measured from the antennas' base plane (far field signal).
• The environment noise is complex uncorrelated circular Gaussian with a power \(  \sigma^2_v \)
• Moreover, other interfering signals impinge with a known measured angle of \( \theta_1 = \frac{2\pi}{3} \)  
• It was also determined that there are other interfering signals as well, with unknown inference angles. 

The process of adaptive cancellation of the MVDR beamformer proved satisfactory for a known interfering signal angle. This way, initial parameters of the filter design can be identified for the adaptive algorithm initialization, based on the classical wiener beamforming filter. The adaptation process can be evidenced on the filter's spatial response function.
Ultimately, the cancelling and selectivity capability of a well designed filter improves with the number of iterations and with a good INR. 
If an unknown angle of an interfering signal is to be accounted for, the initial conditions cannot be determined clearly and the interfering signal results almost unmodified to the filter, impacting negatively on the symbol detection and received signal estimation.

(Details on the algorithm construction and theoretical background considerations soon to be added.)

Adaptation Scheme for an antennae array

Results and Performance analysis

A number of simulations in MATLAB were carried out as to test the filter performance facing varying factors such as environment noise, array size, INR and computational cost and convergence, i.e. number of iterations for a given resolution specification.

Spatial Response with known (estimated) interference signals

A spatial response was plotted for different antennae quantities and SNR, INR merit figures.
It can be seen that the number of iterations smooths the filter response. The number of antennae set the number of equally spaced zeros that can be detected on the first iterations. The simulation results show that the zeros corresponding to erroneous beamforming positions are smoothed out as the number of iteration increases. The more negative the signal to interference ratio i, the more pronounced these zeros are and the filter must reject interfering signals with more intensity.

Spatial response for n=6 iterations (above) and n = 990 (below). SNR = 10 INR = -10 M=10

Spatial response for n=6 iterations (above) and n = 990 (below). SNR = 10 INR = -5 M=10

Spatial response for n=6 iterations (above) and n = 990 (below). SNR = 10 INR = -1

 M=10

Spatial response for n=6 iterations (above) and n = 990 (below). SNR = 20 INR = -5 M=10

Spatial response for n=6 iterations (above) and n = 990 (below). SNR = 20 INR = -5 M=6

Spatial response for n=6 iterations (above) and n = 990 (below). SNR = 20 INR = -10 M=6

Scattering Diagrams for a known interference signal

The scattering symbol diagrams for different array sizes, SNR and INR are shown below. It can be seen that, given that the beamforming filter is well applied the INR, i.e. the signal to interference ratio does not impact in a remarkable way on the filter's performance. Nevertheless, thermal noise has an important impact on the scattering of the received symbols. This is clearly due to the filters selectivity onto a single direction of preference, given by the constraint vector. White noise, on the contrary, impinges equally in all directions, giving a suboptimal approach. This concept will be clarified when the filter is utilized with an unknown received signal. 

Scattering Diagram for SNR = 10, INR = -10 and M = 10

Scattering Diagram for SNR = 10, INR = -5 and M = 10

Scattering Diagram for SNR = 10, INR = -1 and M = 10

Scattering Diagram for SNR = 20, INR = -5 and M = 10

Scattering Diagram for SNR = 20, INR = -5 and M =6

Interference of an unknown signal, unestimated angle of arrival.

Spatial Response

Simulations were carried out to show the filter's performance in the presence of an unknown interference signal.  It can be noted that, due to the absence of a zero on the real incidence angle of the interference signal (approx \( \frac{\pi}{4}\) ), the interfering signal is treated as white, uncorrelated noise. This is particularly notable on high interference signal power (i.e. low INR).

Spatial response for n=6 iterations (above) and n=990 (below). Unknown signal interference angle. SNR = 10, INR = -5, M = 10

Spatial response for n=6 iterations (above) and n=990 (below). Unknown signal interference angle. SNR = 30, INR = -10, M = 10

Scattering Diagrams

It can be seen that the incidence of thermal noise does not affect the filter performance on this case. Nevertheless, the fact that the interference signal angle of incidence is not known impacts negatively on the filter's performance regarding low INR. The filter's rejection power is highly compromised and the symbol detection becomes implausible.

Scattering Diagram for SNR=10 INR = -5 and M = 10. Angle of interfering signal is unknown.

Scattering Diagram for SNR=20 INR = -5 and M = 10. Angle of interfering signal is unknown.

Scattering Diagram for SNR=10 INR = -10 and M = 10. Angle of interfering signal is unknown.

Scattering Diagram for SNR=10 INR = -1 and M = 10. Angle of interfering signal is unknown.

Project: PLL Based Effects Processor, product design and implementation.

Place of Development: CAT Recording Studios/Freelance Engineering Design
Date: November 2011
Duration: 8 weeks
Author: Pablo Manuel Delgado

Description: Phase Locked Loop based effects processor. Original Design.

 The product itself was developed under a "boutique stompbox" framework. Nevertheless, the same circuit and design parameter criteria can be applied to a mass production manufacture line, due to the fact that this design was carried out with a failure rate analysis, quality control, component availability constraints and a Gantt diagram for the associated tasks.






 Sound Sample:

All sounds -except electronic percussion- recorded with a bass guitar through the PLL effects processor. Sample song to show some of the device's capabilities and versatility.

Product Description

The circuit itself is based on a common phase locked loop IC. It utilizes a feedback loop to synchronize an internal oscillator to the fundamental frequency of the input signal, or one of its most prominent harmonics. The oscillator itself acts as a sound wave synthesizer that follows the input signal. The applied input can be any type of signal, i.e. guitar, bass, another synthesizer or line level signal. Its user interface modified parameters are comprised of:

• A Preamp Level: Modifies the preamp level gain in order to provide input signal conditioning for optimal performance.
• A Range control: Modifies the PLL's frequency lock range. The variation of this control provides different synchronization modes of the internal oscillator, changing the processed sound characteristics.
• A Mix knob: Provides a mixing level of the clean and processed signal.
• Volume level
• Envelope Follower switch: A switch that enables a parallel circuit that outputs a rectified control voltage proportional to the input signal level, giving a way of expression dependent of said signal's dynamic range. The control voltage acts over the PLL's range control.

PLL Processor's operating scheme. 

Product Design

Block Diagram

The next figure represents the device's functional block diagram.

The design process consisted in the investigation of convenient topologies, component values, simulation and test benching respectively. The prioritized criterion was to maintain the device as simple as possible, in order to reduce cost and failure rate.

Power Supply



Requirements

Power supply voltage must require sufficient dynamic range to allow full signal excursion and not cause distortion on the signal path. Voltage stabilization is also needed to acquire good oscillator frequency  stability.

\begin{equation}
V_{cc} = +9V ± 5\%
\end{equation}

Solution

An integrated LM7809 regulator  was used, this IC meets all the required specifications. Due to the good characteristics of the regulator, a simple low power transformer can be used to power the unit fro the electrical network. A voltage range from 9v to 14v is sufficient to accomplish the task, and the regulator will take care of the proper conditioning tasks.

Input Stage


Requirements

Its main purpose is to provide signal conditioning, i.e. impedance matching for the different output Thevenin equivalents that input devices can present. Input signals need also bee independent of musical instruments with passive or active sources, or line level inputs from other sound processing devices/consoles with high output impedances.

\begin{equation}
R_g = 15k\Omega to 100 k\Omega
\end{equation}

A gain control is also needed in order to adapt input signal level to guarantee a good signal tracking.

Solution

A follower configuration was chosen composed of an Operational Amplifier and a serial potentiometer to modify the input impedance and the acquired signal level:

\begin {equation}
R_{in} = 20 k\Omega to 100 k\Omega
\end{equation}


Phase Locked Loop



Requirements

A frequency stability of at least 10%  of the input signal's frequency of interest is desired. Also, de capture range must be at least 200 Hz to 10kHz, in order to cover all the possible spectrum characteristics of a fundamental tone of a, say, common musical stringed instrument.

Solution

In terms of the requirements described above and also simplicity and market availability, an integrated solution was proposed for the whole functional block. The CD4046 IC proved sufficient for the desired tasks and specifications. Its main characteristics are:

• Low frequency oscillator thermal stability: 0.04% for each ºC of temperature
• Power supply: 5 to 15V
• Oscillator alinearity: less than 1%
• Capture Range: 10Hz to 1.4Mhz (typical). Controlled by resistive networks.

 Envelope Follower



Requirements

The envelope follower is used to change the capture range parameters of the oscillator. This way a modulation of the input signal is provided depending on the input signal's voltage swing. The main purpose of this inclusion is to provide a mean of expressiveness coming from the instrument that is going to be processed. The envelope follower circuit itself is comprised of a rectifying circuit and an integrator, its time constant was calculated to provide minimum ripple on lower frequencies and to provide a good rectified control signal. 

Solution

The topology chosen for the envelope follower is shown below.

Envelope Follower with optical coupling

 The coupling mode for the control range input of the CD4046 is an optical one. The chosen optocoupler was HF113 FET (optical varying resistor) and it provides the desired transfer characteristics to generate a good control signal based on varying resistance of the equivalent control network applied to the PLL. A current calibration potentiometer is also included, as well as a manual switch that passivises the follower circuit. The resistors were calculated as to have a maximum voltage transfer, as well as a suitable control current for the HF113. The integrator's time constant was approximated by simulation and finally determined in practice:

\begin{equation}
Time = \frac{RC}{2.2} = 2.2 \times 1 \mu F \times 100 k \Omega = 0,22 seg.
\end{equation}



Mixer and Output Stage


Requirements

The output stage must be in charge of providing a correct output impedance for interconnection with other sound processing units, consoles or amplifiers.

\begin{equation}
R_{out} = 100k \Omega
\end{equation}

it is also needed to provide a volume control stage.

Solution

A follower configuration is employed with an operational amplifier and an output potentiometer to implement the volume control. A similar configuration is used to adapt both signals, processed and unprocessed, which paths converge to a linear potentiometer with three terminals,i.e. the mixer control.


Other considerations

Sound Quality

The figure of merit perceived by potential clients as "sound quality" can be translated into a series of quantifiable parameters:

• Noise immunity performance
• Line interference rejection (i.e. 50 or 60Hz) and humming
• Low interstage distiortion
• A sufficient dynamic range of operation in order to avoid signal saturation and unwanted peaks
• Bootstraping of the unprocessed signal, i.e. maintain the unprocessed signal as clean as possible

 All these requirements are met by utilizing high performance integrated rectifiers for the power supply such as the LM7809.
The operational amplifiers chosen (TL072) resulted in a critical component on the test bench, due to its good noise immunity and signal performance. The dynamic range is that of 0V to 9V with an operating bias point of 4.5V for symmetry.
The coupling capacitors are electrolytic and ceramic ones of low tolerance. These are commonly used on the industry as this equipments does not pretend to be a high fidelity audio amplification unit.


Schematic Diagram

 



PCB Layout

PCB Layout and component distribution

Polarity inversion protection circuit

The most important element at the time of determining the failure rate was  the LM7809 to provide stability for the oscillator. This regulator provides low failure rates given that accidental polarity inversion is not produced. An improper borne connection or transformer polarity could cause overheating, destroying the regulator's circuits in just a few seconds.

A simple diode voltage inversion protection was implemented

Polarity inversion circuit

 Mechanical Design